Hallo @ll zusammen,
leider bootet meine Box nicht mehr 
Ich hatte gboot.bin installiert und jetzt ladet die Box nur noch bis zum Boollogo.
Über den Rescue habe ich vom Feed eine neue Image zu flashen, aber das Problem belibt
Telnetverbindung habe ich nur im Rescue Modus und auch keine FTP.
Was kann ich machen?
Ich hänge hier noch das Boot-log mit an
02 01: 00
03 04: 00 00 3a b0
06 08: 32 30 32 30 30 36 31 33
07 0f: 34 36 31 33 32 35 30 30 30 30 31 35 30 32 34
05 04: 01 01 01 01
08 01: 00
04 06: 00 09 34 4b 43 ac
10 08: c4 c3 63 34 07 05 8d 96
11 10: 18 0b cf f3 17 44 ca 8f 9f 17 e6 7c 1a c3 91 58
ff 01: 38
card out
** Bad device mmc 0 **
cannot get sdcard label
739 bytes read in 4 ms (179.7 KiB/s)
## Executing script at 01080000
1843270 bytes read in 30 ms (58.6 MiB/s)
[OSD]load fb addr from dts:/meson-fb
[OSD]set initrd_high: 0x7f800000
[OSD]fb_addr for logo: 0x7f800000
[OSD]load fb addr from dts:/meson-fb
[OSD]fb_addr for logo: 0x7f800000
[OSD]VPP_OFIFO_SIZE:0xfff01fff
[CANVAS]canvas init
[CANVAS]addr=0x7f800000 width=2560, height=1440
[OSD]wait_vsync_wakeup exit
[OSD]osd_hw.free_dst_data: 0,1919,0,1079
[OSD]osd1_update_disp_freescale_enable
[OSD]wait_vsync_wakeup exit
[OSD]wait_vsync_wakeup exit
[OSD]wait_vsync_wakeup exit
cvbs: outputmode[1080p50hz] is invalid
vpp: vpp_matrix_update: 2
set hdmitx VIC = 31
config HPLL = 4455000 frac_rate = 0
HPLL: 0x3b0004b9
HPLL: 0x1b0004b9
HPLL: 0xdb0004b9
config HPLL done
j = 6 vid_clk_div = 1
hdmitx phy setting done
hdmitx: set enc for VIC: 31
enc_vpu_bridge_reset[1216]
rx version is 1.4 or below div=10
Normal bootup
Net: dwmac.ff3f0000
Hit Enter or space or Ctrl+C key to stop autoboot -- : 0
card out
** Bad device mmc 0 **
dreambox_two<INTERRUPT>
dreambox_two#
bl2_stage_init 0x01
bl2_stage_init 0x81
hw id: 0x0000 - pwm id 0x01
bl2_stage_init 0xc1
bl2_stage_init 0x02
L0:e033003f
L1:00000703
L2:0000c067
L3:14000020
B2:00433060
B1:f0c021b0
TE: 659048
BL2 Built : 15:17:18, Feb 20 2019. g12b gb91a9c0 - jenkins@walle02Ysh
Board ID = 2
Set A53 clk to 24M
Set A73 clk to 24M
Set clk81 to 24M
A53 clk: 1200 MHz
A73 clk: 1200 MHz
CLK81: 166.6M
smccc: 000a1afd
eMMC boot @ 0
sw8 s
sd/emmc cmd 8 arg 0x00000000 status 01ff3000
DDR driver_vesion: LPDDR4_PHY_V_0_1_11 build time: Feb 20 2019 15:17:14
board id: 2
Load FIP HDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
fw parse done
Load ddrfw from eMMC, src: 0x00014200, des: 0xfffd0000, size: 0x0000c000, part: 0
Load ddrfw from eMMC, src: 0x00068200, des: 0xfffd0000, size: 0x00004000, part: 0
PIEI prepare done
Cfg max: 4, cur: 1. Board id: 255. Force loop cfg
DDR4 probe
ddr clk to 1200MHz
Load ddrfw from eMMC, src: 0x0002c200, des: 0xfffd0000, size: 0x0000c000, part: 0
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : End of read dq deskew training
INFO : End of MPR read delay center optimization
INFO : End of Write leveling coarse delay
INFO : End of write delay center optimization
INFO : End of read delay center optimization
INFO : End of max read latency training
INFO : Training has run successfully!
1D training succeed
Load ddrfw from eMMC, src: 0x00038200, des: 0xfffd0000, size: 0x0000c000, part: 0
Check phy result
INFO : End of initialization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : Training has run successfully!
R0_RxClkDly_Margin==104 ps 8
R0_TxDqDly_Margi==156 ps 12
R1_RxClkDly_Margin==0 ps 0
R1_TxDqDly_Margi==0 ps 0
dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0001
ddr scramble enable
2D training succeed
auto size-- 65535DDR cs0 size: 2048MB
DDR cs1 size: 0MB
DMC_DDR_CTRL: 0040002cDDR size: 2048MB
cs0 DataBus test pass
cs0 AddrBus test pass
pre test bdlr_100_average==484 bdlr_100_min==484 bdlr_100_max==484 bdlr_100_cur==484
aft test bdlr_100_average==484 bdlr_100_min==484 bdlr_100_max==484 bdlr_100_cur==484
100bdlr_step_size ps== 490
result report
boot times 0
non-sec scramble use zero key
ddr scramble enabled
Enable ddr reg access
00000000
emmc switch 3 ok
Authentication key not yet programmed
get rpmb counter error 0x00000007
00000000
emmc switch 0 ok
Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
Load BL3X from eMMC, src: 0x0006c200, des: 0x0175c000, size: 0x0018c000, part: 0
0.0;0.0;M3 CHK:0;bl30 start
run into bl31
NOTICE: BL31: v1.3(release):bee21ef
NOTICE: BL31: Built : 16:42:55, Feb 21 2019
NOTICE: BL31: G12A secure boot!
INFO: BL3-2: ATOS-V2.4-202-g7b21f5e #1 Fri Dec 21 01:30:01 UTC 2018 arm
INFO: BL3-2: Chip: Unknown Rev: A (29:A - 40:2)
INFO: BL3-2: crypto engine DMA
INFO: BL3-2: secure time TEE
INFO: BL3-2: CONFIG_DEVICE_SECURE 0xb200000e
U-Boot 2015.01-g51a5912146 (Feb 27 2020 - 01:52:35)
DRAM: 2 GiB
Relocation Offset is: 76e6d000
spi_post_bind(spicc): req_seq = 0
spi_post_bind(spifc): req_seq = 1
register usb cfg[0][1] = 0000000077f54220
MMC: dm one emmc init
.
aml_priv->desc_buf = 0x0000000073e5d7b0
aml_priv->desc_buf = 0x0000000073e5faf0
SDIO Port B: 0, SDIO Port C: 1
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
emmc/sd response timeout, cmd8, status=0x1ff2800
emmc/sd response timeout, cmd55, status=0x1ff2800
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x1, tx-dly 0, clock 40000000
aml_sd_retry_refix[983]:delay = 0x0,gadjust =0x52000
[mmc_startup] mmc refix success
init_part() 297: PART_TYPE_AML
[mmc_init] mmc init success
skip dtb signature check
start dts,buffer=0000000073e62360,dt_addr=0000000073e62360
get_partition_from_dts() 71: ret 0
parts: 4
00: recovery 0000000004000000 1
01: boot 0000000002000000 1
set has_boot_slot = 0
02:dreambox-rootfs 0000000100000000 1
03:dreambox-data ffffffffffffffff 4
init_part() 297: PART_TYPE_AML
eMMC/TSD partition table have been checked OK!
crc32_s:0x1577dad == storage crc_pattern:0x1577dad!!!
crc32_s:0xee152b83 == storage crc_pattern:0xee152b83!!!
crc32_s:0x7fd3b243 == storage crc_pattern:0x7fd3b243!!!
mmc env offset: 0x7400000
In: serial
Out: serial
Err: serial
reboot_mode=cold_boot
itest - return true/false on integer compare
Usage:
itest [.b, .w, .l, .s] [*]value1 <op> [*]value2
[store]To run cmd[emmc dtb_read 0x1000000 0x40000]
_verify_dtb_checksum()-2755: calc 1cc15c8c, store 1cc15c8c
_verify_dtb_checksum()-2755: calc 1cc15c8c, store 1cc15c8c
dtb_read()-2972: total valid 2
update_old_dtb()-2953: do nothing
amlkey_init() enter!
[EFUSE_ERR]f(efuse_usr_api_init_dtb)L60:not find /efusekey node [FDT_ERR_NOTFOUND].
[KM]Error:f[keymanage_efuse_init]L38:efuse init failed
[KM]Error:f[key_unify_init]L177:Device[1] init failed, err=39
vpu: clk_level in dts: 7
vpu: vpu_power_on
vpu: set clk: 666667000Hz, readback: 666666667Hz(0x100)
vpu: vpu_module_init_config
vpp: vpp_init
vpp: g12a/b osd1 matrix rgb2yuv ..............
vpp: g12a/b osd2 matrix rgb2yuv..............
vpp: g12a/b osd3 matrix rgb2yuv..............
cvbs: cpuid:0x29
lcd: error: not find /backlight node: FDT_ERR_NOTFOUND
lcd: error: failed to get key_valid
lcd: detect mode: tablet, key_valid: 0
lcd: failed to get lcd_cpu_gpio_names
lcd: load config from dts
lcd: pinctrl_version: 2
lcd: use panel_type=lcd_5
lcd extern: load config from dts
lcd extern: add driver mipi_default(0)
lcd extern: aml_lcd_extern_probe ok
lcd: bl: no backlight exist
set lcd bl to 0
set lcd bl to 200
tpm activate
01 01: 19
02 01: 00
03 04: 00 00 3a b0
06 08: 32 30 32 30 30 36 31 33
07 0f: 34 36 31 33 32 35 30 30 30 30 31 35 30 32 34
05 04: 01 01 01 01
08 01: 00
04 06: 00 09 34 4b 43 ac
10 08: c4 c3 63 34 07 05 8d 96
11 10: 18 0b cf f3 17 44 ca 8f 9f 17 e6 7c 1a c3 91 58
ff 01: 38
card out
** Bad device mmc 0 **
cannot get sdcard label
739 bytes read in 3 ms (240.2 KiB/s)
## Executing script at 01080000
1843270 bytes read in 30 ms (58.6 MiB/s)
[OSD]load fb addr from dts:/meson-fb
[OSD]set initrd_high: 0x7f800000
[OSD]fb_addr for logo: 0x7f800000
[OSD]load fb addr from dts:/meson-fb
[OSD]fb_addr for logo: 0x7f800000
[OSD]VPP_OFIFO_SIZE:0xfff01fff
[CANVAS]canvas init
[CANVAS]addr=0x7f800000 width=2560, height=1440
[OSD]wait_vsync_wakeup exit
[OSD]osd_hw.free_dst_data: 0,1919,0,1079
[OSD]osd1_update_disp_freescale_enable
[OSD]wait_vsync_wakeup exit
[OSD]wait_vsync_wakeup exit
[OSD]wait_vsync_wakeup exit
cvbs: outputmode[1080p50hz] is invalid
vpp: vpp_matrix_update: 2
set hdmitx VIC = 31
config HPLL = 4455000 frac_rate = 0
HPLL: 0x3b0004b9
HPLL: 0x1b0004b9
HPLL: 0xdb0004b9
config HPLL done
j = 6 vid_clk_div = 1
hdmitx phy setting done
hdmitx: set enc for VIC: 31
enc_vpu_bridge_reset[1216]
rx version is 1.4 or below div=10
Normal bootup
Net: dwmac.ff3f0000
Hit Enter or space or Ctrl+C key to stop autoboot -- : 0
card out
** Bad device mmc 0 **
dreambox_two#Und jetzt mit SD-Card
02 01: 00
03 04: 00 00 3a b0
06 08: 32 30 32 30 30 36 31 33
07 0f: 34 36 31 33 32 35 30 30 30 30 31 35 30 32 34
05 04: 01 01 01 01
08 01: 00
04 06: 00 09 34 4b 43 ac
10 08: c4 c3 63 34 07 05 8d 96
11 10: 18 0b cf f3 17 44 ca 8f 9f 17 e6 7c 1a c3 91 58
ff 01: 38
card out
** Bad device mmc 0 **
cannot get sdcard label
739 bytes read in 4 ms (179.7 KiB/s)
## Executing script at 01080000
1843270 bytes read in 30 ms (58.6 MiB/s)
[OSD]load fb addr from dts:/meson-fb
[OSD]set initrd_high: 0x7f800000
[OSD]fb_addr for logo: 0x7f800000
[OSD]load fb addr from dts:/meson-fb
[OSD]fb_addr for logo: 0x7f800000
[OSD]VPP_OFIFO_SIZE:0xfff01fff
[CANVAS]canvas init
[CANVAS]addr=0x7f800000 width=2560, height=1440
[OSD]wait_vsync_wakeup exit
[OSD]osd_hw.free_dst_data: 0,1919,0,1079
[OSD]osd1_update_disp_freescale_enable
[OSD]wait_vsync_wakeup exit
[OSD]wait_vsync_wakeup exit
[OSD]wait_vsync_wakeup exit
cvbs: outputmode[1080p50hz] is invalid
vpp: vpp_matrix_update: 2
set hdmitx VIC = 31
config HPLL = 4455000 frac_rate = 0
HPLL: 0x3b0004b9
HPLL: 0x1b0004b9
HPLL: 0xdb0004b9
config HPLL done
j = 6 vid_clk_div = 1
hdmitx phy setting done
hdmitx: set enc for VIC: 31
enc_vpu_bridge_reset[1216]
rx version is 1.4 or below div=10
Normal bootup
Net: dwmac.ff3f0000
Hit Enter or space or Ctrl+C key to stop autoboot -- : 0
card out
** Bad device mmc 0 **
dreambox_two<INTERRUPT>
dreambox_two#
bl2_stage_init 0x01
bl2_stage_init 0x81
hw id: 0x0000 - pwm id 0x01
bl2_stage_init 0xc1
bl2_stage_init 0x02
L0:e033003f
L1:00000703
L2:0000c067
L3:14000020
B2:00433060
B1:f0c021b0
TE: 659048
BL2 Built : 15:17:18, Feb 20 2019. g12b gb91a9c0 - jenkins@walle02Ysh
Board ID = 2
Set A53 clk to 24M
Set A73 clk to 24M
Set clk81 to 24M
A53 clk: 1200 MHz
A73 clk: 1200 MHz
CLK81: 166.6M
smccc: 000a1afd
eMMC boot @ 0
sw8 s
sd/emmc cmd 8 arg 0x00000000 status 01ff3000
DDR driver_vesion: LPDDR4_PHY_V_0_1_11 build time: Feb 20 2019 15:17:14
board id: 2
Load FIP HDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
fw parse done
Load ddrfw from eMMC, src: 0x00014200, des: 0xfffd0000, size: 0x0000c000, part: 0
Load ddrfw from eMMC, src: 0x00068200, des: 0xfffd0000, size: 0x00004000, part: 0
PIEI prepare done
Cfg max: 4, cur: 1. Board id: 255. Force loop cfg
DDR4 probe
ddr clk to 1200MHz
Load ddrfw from eMMC, src: 0x0002c200, des: 0xfffd0000, size: 0x0000c000, part: 0
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : End of read dq deskew training
INFO : End of MPR read delay center optimization
INFO : End of Write leveling coarse delay
INFO : End of write delay center optimization
INFO : End of read delay center optimization
INFO : End of max read latency training
INFO : Training has run successfully!
1D training succeed
Load ddrfw from eMMC, src: 0x00038200, des: 0xfffd0000, size: 0x0000c000, part: 0
Check phy result
INFO : End of initialization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : Training has run successfully!
R0_RxClkDly_Margin==104 ps 8
R0_TxDqDly_Margi==156 ps 12
R1_RxClkDly_Margin==0 ps 0
R1_TxDqDly_Margi==0 ps 0
dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0001
ddr scramble enable
2D training succeed
auto size-- 65535DDR cs0 size: 2048MB
DDR cs1 size: 0MB
DMC_DDR_CTRL: 0040002cDDR size: 2048MB
cs0 DataBus test pass
cs0 AddrBus test pass
pre test bdlr_100_average==484 bdlr_100_min==484 bdlr_100_max==484 bdlr_100_cur==484
aft test bdlr_100_average==484 bdlr_100_min==484 bdlr_100_max==484 bdlr_100_cur==484
100bdlr_step_size ps== 490
result report
boot times 0
non-sec scramble use zero key
ddr scramble enabled
Enable ddr reg access
00000000
emmc switch 3 ok
Authentication key not yet programmed
get rpmb counter error 0x00000007
00000000
emmc switch 0 ok
Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
Load BL3X from eMMC, src: 0x0006c200, des: 0x0175c000, size: 0x0018c000, part: 0
0.0;0.0;M3 CHK:0;bl30 start
run into bl31
NOTICE: BL31: v1.3(release):bee21ef
NOTICE: BL31: Built : 16:42:55, Feb 21 2019
NOTICE: BL31: G12A secure boot!
INFO: BL3-2: ATOS-V2.4-202-g7b21f5e #1 Fri Dec 21 01:30:01 UTC 2018 arm
INFO: BL3-2: Chip: Unknown Rev: A (29:A - 40:2)
INFO: BL3-2: crypto engine DMA
INFO: BL3-2: secure time TEE
INFO: BL3-2: CONFIG_DEVICE_SECURE 0xb200000e
U-Boot 2015.01-g51a5912146 (Feb 27 2020 - 01:52:35)
DRAM: 2 GiB
Relocation Offset is: 76e6d000
spi_post_bind(spicc): req_seq = 0
spi_post_bind(spifc): req_seq = 1
register usb cfg[0][1] = 0000000077f54220
MMC: dm one emmc init
.
aml_priv->desc_buf = 0x0000000073e5d7b0
aml_priv->desc_buf = 0x0000000073e5faf0
SDIO Port B: 0, SDIO Port C: 1
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
emmc/sd response timeout, cmd8, status=0x1ff2800
emmc/sd response timeout, cmd55, status=0x1ff2800
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x1, tx-dly 0, clock 40000000
aml_sd_retry_refix[983]:delay = 0x0,gadjust =0x52000
[mmc_startup] mmc refix success
init_part() 297: PART_TYPE_AML
[mmc_init] mmc init success
skip dtb signature check
start dts,buffer=0000000073e62360,dt_addr=0000000073e62360
get_partition_from_dts() 71: ret 0
parts: 4
00: recovery 0000000004000000 1
01: boot 0000000002000000 1
set has_boot_slot = 0
02:dreambox-rootfs 0000000100000000 1
03:dreambox-data ffffffffffffffff 4
init_part() 297: PART_TYPE_AML
eMMC/TSD partition table have been checked OK!
crc32_s:0x1577dad == storage crc_pattern:0x1577dad!!!
crc32_s:0xee152b83 == storage crc_pattern:0xee152b83!!!
crc32_s:0x7fd3b243 == storage crc_pattern:0x7fd3b243!!!
mmc env offset: 0x7400000
In: serial
Out: serial
Err: serial
reboot_mode=cold_boot
itest - return true/false on integer compare
Usage:
itest [.b, .w, .l, .s] [*]value1 <op> [*]value2
[store]To run cmd[emmc dtb_read 0x1000000 0x40000]
_verify_dtb_checksum()-2755: calc 1cc15c8c, store 1cc15c8c
_verify_dtb_checksum()-2755: calc 1cc15c8c, store 1cc15c8c
dtb_read()-2972: total valid 2
update_old_dtb()-2953: do nothing
amlkey_init() enter!
[EFUSE_ERR]f(efuse_usr_api_init_dtb)L60:not find /efusekey node [FDT_ERR_NOTFOUND].
[KM]Error:f[keymanage_efuse_init]L38:efuse init failed
[KM]Error:f[key_unify_init]L177:Device[1] init failed, err=39
vpu: clk_level in dts: 7
vpu: vpu_power_on
vpu: set clk: 666667000Hz, readback: 666666667Hz(0x100)
vpu: vpu_module_init_config
vpp: vpp_init
vpp: g12a/b osd1 matrix rgb2yuv ..............
vpp: g12a/b osd2 matrix rgb2yuv..............
vpp: g12a/b osd3 matrix rgb2yuv..............
cvbs: cpuid:0x29
lcd: error: not find /backlight node: FDT_ERR_NOTFOUND
lcd: error: failed to get key_valid
lcd: detect mode: tablet, key_valid: 0
lcd: failed to get lcd_cpu_gpio_names
lcd: load config from dts
lcd: pinctrl_version: 2
lcd: use panel_type=lcd_5
lcd extern: load config from dts
lcd extern: add driver mipi_default(0)
lcd extern: aml_lcd_extern_probe ok
lcd: bl: no backlight exist
set lcd bl to 0
set lcd bl to 200
tpm activate
01 01: 19
02 01: 00
03 04: 00 00 3a b0
06 08: 32 30 32 30 30 36 31 33
07 0f: 34 36 31 33 32 35 30 30 30 30 31 35 30 32 34
05 04: 01 01 01 01
08 01: 00
04 06: 00 09 34 4b 43 ac
10 08: c4 c3 63 34 07 05 8d 96
11 10: 18 0b cf f3 17 44 ca 8f 9f 17 e6 7c 1a c3 91 58
ff 01: 38
card out
** Bad device mmc 0 **
cannot get sdcard label
739 bytes read in 3 ms (240.2 KiB/s)
## Executing script at 01080000
1843270 bytes read in 30 ms (58.6 MiB/s)
[OSD]load fb addr from dts:/meson-fb
[OSD]set initrd_high: 0x7f800000
[OSD]fb_addr for logo: 0x7f800000
[OSD]load fb addr from dts:/meson-fb
[OSD]fb_addr for logo: 0x7f800000
[OSD]VPP_OFIFO_SIZE:0xfff01fff
[CANVAS]canvas init
[CANVAS]addr=0x7f800000 width=2560, height=1440
[OSD]wait_vsync_wakeup exit
[OSD]osd_hw.free_dst_data: 0,1919,0,1079
[OSD]osd1_update_disp_freescale_enable
[OSD]wait_vsync_wakeup exit
[OSD]wait_vsync_wakeup exit
[OSD]wait_vsync_wakeup exit
cvbs: outputmode[1080p50hz] is invalid
vpp: vpp_matrix_update: 2
set hdmitx VIC = 31
config HPLL = 4455000 frac_rate = 0
HPLL: 0x3b0004b9
HPLL: 0x1b0004b9
HPLL: 0xdb0004b9
config HPLL done
j = 6 vid_clk_div = 1
hdmitx phy setting done
hdmitx: set enc for VIC: 31
enc_vpu_bridge_reset[1216]
rx version is 1.4 or below div=10
Normal bootup
Net: dwmac.ff3f0000
Hit Enter or space or Ctrl+C key to stop autoboot -- : 0
card out
** Bad device mmc 0 **
dreambox_two#
bl2_stage_init 0x01
bl2_stage_init 0x81
hw id: 0x0000 - pwm id 0x01
bl2_stage_init 0xc1
bl2_stage_init 0x02
L0:e033003f
L1:00000703
L2:0000c067
L3:14000020
B2:00433060
B1:f0c021b0
TE: 638370
BL2 Built : 15:17:18, Feb 20 2019. g12b gb91a9c0 - jenkins@walle02Ysh
Board ID = 2
Set A53 clk to 24M
Set A73 clk to 24M
Set clk81 to 24M
A53 clk: 1200 MHz
A73 clk: 1200 MHz
CLK81: 166.6M
smccc: 0009ca39
eMMC boot @ 0
sw8 s
sd/emmc cmd 8 arg 0x00000000 status 01ff3000
DDR driver_vesion: LPDDR4_PHY_V_0_1_11 build time: Feb 20 2019 15:17:14
board id: 2
Load FIP HDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
fw parse done
Load ddrfw from eMMC, src: 0x00014200, des: 0xfffd0000, size: 0x0000c000, part: 0
Load ddrfw from eMMC, src: 0x00068200, des: 0xfffd0000, size: 0x00004000, part: 0
PIEI prepare done
Cfg max: 4, cur: 1. Board id: 255. Force loop cfg
DDR4 probe
ddr clk to 1200MHz
Load ddrfw from eMMC, src: 0x0002c200, des: 0xfffd0000, size: 0x0000c000, part: 0
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : End of read dq deskew training
INFO : End of MPR read delay center optimization
INFO : End of Write leveling coarse delay
INFO : End of write delay center optimization
INFO : End of read delay center optimization
INFO : End of max read latency training
INFO : Training has run successfully!
1D training succeed
Load ddrfw from eMMC, src: 0x00038200, des: 0xfffd0000, size: 0x0000c000, part: 0
Check phy result
INFO : End of initialization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : Training has run successfully!
R0_RxClkDly_Margin==117 ps 9
R0_TxDqDly_Margi==156 ps 12
R1_RxClkDly_Margin==0 ps 0
R1_TxDqDly_Margi==0 ps 0
dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0001
ddr scramble enable
2D training succeed
auto size-- 65535DDR cs0 size: 2048MB
DDR cs1 size: 0MB
DMC_DDR_CTRL: 0040002cDDR size: 2048MB
cs0 DataBus test pass
cs0 AddrBus test pass
pre test bdlr_100_average==490 bdlr_100_min==490 bdlr_100_max==490 bdlr_100_cur==490
aft test bdlr_100_average==490 bdlr_100_min==490 bdlr_100_max==490 bdlr_100_cur==490
100bdlr_step_size ps== 484
result report
boot times 0
non-sec scramble use zero key
ddr scramble enabled
Enable ddr reg access
00000000
emmc switch 3 ok
Authentication key not yet programmed
get rpmb counter error 0x00000007
00000000
emmc switch 0 ok
Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
Load BL3X from eMMC, src: 0x0006c200, des: 0x0175c000, size: 0x0018c000, part: 0
0.0;0.0;M3 CHK:0;bl30 start
run into bl31
NOTICE: BL31: v1.3(release):bee21ef
NOTICE: BL31: Built : 16:42:55, Feb 21 2019
NOTICE: BL31: G12A secure boot!
INFO: BL3-2: ATOS-V2.4-202-g7b21f5e #1 Fri Dec 21 01:30:01 UTC 2018 arm
INFO: BL3-2: Chip: Unknown Rev: A (29:A - 40:2)
INFO: BL3-2: crypto engine DMA
INFO: BL3-2: secure time TEE
INFO: BL3-2: CONFIG_DEVICE_SECURE 0xb200000e
U-Boot 2015.01-g51a5912146 (Feb 27 2020 - 01:52:35)
DRAM: 2 GiB
Relocation Offset is: 76e6d000
spi_post_bind(spicc): req_seq = 0
spi_post_bind(spifc): req_seq = 1
register usb cfg[0][1] = 0000000077f54220
MMC: dm one emmc init
.
aml_priv->desc_buf = 0x0000000073e5d7b0
aml_priv->desc_buf = 0x0000000073e5faf0
SDIO Port B: 0, SDIO Port C: 1
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
emmc/sd response timeout, cmd8, status=0x1ff2800
emmc/sd response timeout, cmd55, status=0x1ff2800
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x1, tx-dly 0, clock 40000000
aml_sd_retry_refix[983]:delay = 0x0,gadjust =0x52000
[mmc_startup] mmc refix success
init_part() 297: PART_TYPE_AML
[mmc_init] mmc init success
skip dtb signature check
start dts,buffer=0000000073e62360,dt_addr=0000000073e62360
get_partition_from_dts() 71: ret 0
parts: 4
00: recovery 0000000004000000 1
01: boot 0000000002000000 1
set has_boot_slot = 0
02:dreambox-rootfs 0000000100000000 1
03:dreambox-data ffffffffffffffff 4
init_part() 297: PART_TYPE_AML
eMMC/TSD partition table have been checked OK!
crc32_s:0x1577dad == storage crc_pattern:0x1577dad!!!
crc32_s:0xee152b83 == storage crc_pattern:0xee152b83!!!
crc32_s:0x7fd3b243 == storage crc_pattern:0x7fd3b243!!!
mmc env offset: 0x7400000
In: serial
Out: serial
Err: serial
reboot_mode=cold_boot
itest - return true/false on integer compare
Usage:
itest [.b, .w, .l, .s] [*]value1 <op> [*]value2
[store]To run cmd[emmc dtb_read 0x1000000 0x40000]
_verify_dtb_checksum()-2755: calc 1cc15c8c, store 1cc15c8c
_verify_dtb_checksum()-2755: calc 1cc15c8c, store 1cc15c8c
dtb_read()-2972: total valid 2
update_old_dtb()-2953: do nothing
amlkey_init() enter!
[EFUSE_ERR]f(efuse_usr_api_init_dtb)L60:not find /efusekey node [FDT_ERR_NOTFOUND].
[KM]Error:f[keymanage_efuse_init]L38:efuse init failed
[KM]Error:f[key_unify_init]L177:Device[1] init failed, err=39
vpu: clk_level in dts: 7
vpu: vpu_power_on
vpu: set clk: 666667000Hz, readback: 666666667Hz(0x100)
vpu: vpu_module_init_config
vpp: vpp_init
vpp: g12a/b osd1 matrix rgb2yuv ..............
vpp: g12a/b osd2 matrix rgb2yuv..............
vpp: g12a/b osd3 matrix rgb2yuv..............
cvbs: cpuid:0x29
lcd: error: not find /backlight node: FDT_ERR_NOTFOUND
lcd: error: failed to get key_valid
lcd: detect mode: tablet, key_valid: 0
lcd: failed to get lcd_cpu_gpio_names
lcd: load config from dts
lcd: pinctrl_version: 2
lcd: use panel_type=lcd_5
lcd extern: load config from dts
lcd extern: add driver mipi_default(0)
lcd extern: aml_lcd_extern_probe ok
lcd: bl: no backlight exist
set lcd bl to 0
set lcd bl to 200
tpm activate
01 01: 19
02 01: 00
03 04: 00 00 3a b0
06 08: 32 30 32 30 30 36 31 33
07 0f: 34 36 31 33 32 35 30 30 30 30 31 35 30 32 34
05 04: 01 01 01 01
08 01: 00
04 06: 00 09 34 4b 43 ac
10 08: c4 c3 63 34 07 05 8d 96
11 10: 18 0b cf f3 17 44 ca 8f 9f 17 e6 7c 1a c3 91 58
ff 01: 38
card in
co-phase 0x2, tx-dly 0, clock 400000
co-phase 0x2, tx-dly 0, clock 400000
co-phase 0x2, tx-dly 0, clock 400000
emmc/sd response timeout, cmd8, status=0x1ff2800
emmc/sd response timeout, cmd55, status=0x1ff2800
emmc/sd response timeout, cmd1, status=0x1ff2800
** Bad device mmc 0 **
cannot get sdcard label
739 bytes read in 4 ms (179.7 KiB/s)
## Executing script at 01080000
1843270 bytes read in 30 ms (58.6 MiB/s)
[OSD]load fb addr from dts:/meson-fb
[OSD]set initrd_high: 0x7f800000
[OSD]fb_addr for logo: 0x7f800000
[OSD]load fb addr from dts:/meson-fb
[OSD]fb_addr for logo: 0x7f800000
[OSD]VPP_OFIFO_SIZE:0xfff01fff
[CANVAS]canvas init
[CANVAS]addr=0x7f800000 width=2560, height=1440
[OSD]wait_vsync_wakeup exit
[OSD]osd_hw.free_dst_data: 0,1919,0,1079
[OSD]osd1_update_disp_freescale_enable
[OSD]wait_vsync_wakeup exit
[OSD]wait_vsync_wakeup exit
[OSD]wait_vsync_wakeup exit
cvbs: outputmode[1080p50hz] is invalid
vpp: vpp_matrix_update: 2
set hdmitx VIC = 31
config HPLL = 4455000 frac_rate = 0
HPLL: 0x3b0004b9
HPLL: 0x1b0004b9
HPLL: 0xdb0004b9
config HPLL done
j = 6 vid_clk_div = 1
hdmitx phy setting done
hdmitx: set enc for VIC: 31
enc_vpu_bridge_reset[1216]
rx version is 1.4 or below div=10
Normal bootup
Net: dwmac.ff3f0000
Hit Enter or space or Ctrl+C key to stop autoboot -- : 0
co-phase 0x2, tx-dly 0, clock 400000
co-phase 0x2, tx-dly 0, clock 400000
co-phase 0x2, tx-dly 0, clock 400000
emmc/sd response timeout, cmd8, status=0x1ff2800
emmc/sd response timeout, cmd55, status=0x1ff2800
emmc/sd response timeout, cmd1, status=0x1ff2800
** Bad device mmc 0 **
dreambox_two#
bl2_stage_init 0x01
bl2_stage_init 0x81
hw id: 0x0000 - pwm id 0x01
bl2_stage_init 0xc1
bl2_stage_init 0x02
L0:e033003f
L1:00000703
L2:0000c067
L3:14000020
B2:00433060
B1:f0c021b0
TE: 625851
BL2 Built : 15:17:18, Feb 20 2019. g12b gb91a9c0 - jenkins@walle02Ysh
Board ID = 2
Set A53 clk to 24M
Set A73 clk to 24M
Set clk81 to 24M
A53 clk: 1200 MHz
A73 clk: 1200 MHz
CLK81: 166.6M
smccc: 00099953
eMMC boot @ 0
sw8 s
sd/emmc cmd 8 arg 0x00000000 status 01ff3000
DDR driver_vesion: LPDDR4_PHY_V_0_1_11 build time: Feb 20 2019 15:17:14
board id: 2
Load FIP HDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
fw parse done
Load ddrfw from eMMC, src: 0x00014200, des: 0xfffd0000, size: 0x0000c000, part: 0
Load ddrfw from eMMC, src: 0x00068200, des: 0xfffd0000, size: 0x00004000, part: 0
PIEI prepare done
Cfg max: 4, cur: 1. Board id: 255. Force loop cfg
DDR4 probe
ddr clk to 1200MHz
Load ddrfw from eMMC, src: 0x0002c200, des: 0xfffd0000, size: 0x0000c000, part: 0
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : End of read dq deskew training
INFO : End of MPR read delay center optimization
INFO : End of Write leveling coarse delay
INFO : End of write delay center optimization
INFO : End of read delay center optimization
INFO : End of max read latency training
INFO : Training has run successfully!
1D training succeed
Load ddrfw from eMMC, src: 0x00038200, des: 0xfffd0000, size: 0x0000c000, part: 0
Check phy result
INFO : End of initialization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : Training has run successfully!
R0_RxClkDly_Margin==104 ps 8
R0_TxDqDly_Margi==156 ps 12
R1_RxClkDly_Margin==0 ps 0
R1_TxDqDly_Margi==0 ps 0
dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0001
ddr scramble enable
2D training succeed
auto size-- 65535DDR cs0 size: 2048MB
DDR cs1 size: 0MB
DMC_DDR_CTRL: 0040002cDDR size: 2048MB
cs0 DataBus test pass
cs0 AddrBus test pass
pre test bdlr_100_average==484 bdlr_100_min==484 bdlr_100_max==484 bdlr_100_cur==484
aft test bdlr_100_average==484 bdlr_100_min==484 bdlr_100_max==484 bdlr_100_cur==484
100bdlr_step_size ps== 490
result report
boot times 0
non-sec scramble use zero key
ddr scramble enabled
Enable ddr reg access
00000000
emmc switch 3 ok
Authentication key not yet programmed
get rpmb counter error 0x00000007
00000000
emmc switch 0 ok
Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
Load BL3X from eMMC, src: 0x0006c200, des: 0x0175c000, size: 0x0018c000, part: 0
0.0;0.0;M3 CHK:0;bl30 start
run into bl31
NOTICE: BL31: v1.3(release):bee21ef
NOTICE: BL31: Built : 16:42:55, Feb 21 2019
NOTICE: BL31: G12A secure boot!
INFO: BL3-2: ATOS-V2.4-202-g7b21f5e #1 Fri Dec 21 01:30:01 UTC 2018 arm
INFO: BL3-2: Chip: Unknown Rev: A (29:A - 40:2)
INFO: BL3-2: crypto engine DMA
INFO: BL3-2: secure time TEE
INFO: BL3-2: CONFIG_DEVICE_SECURE 0xb200000e
U-Boot 2015.01-g51a5912146 (Feb 27 2020 - 01:52:35)
DRAM: 2 GiB
Relocation Offset is: 76e6d000
spi_post_bind(spicc): req_seq = 0
spi_post_bind(spifc): req_seq = 1
register usb cfg[0][1] = 0000000077f54220
MMC: dm one emmc init
.
aml_priv->desc_buf = 0x0000000073e5d7b0
aml_priv->desc_buf = 0x0000000073e5faf0
SDIO Port B: 0, SDIO Port C: 1
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
emmc/sd response timeout, cmd8, status=0x1ff2800
emmc/sd response timeout, cmd55, status=0x1ff2800
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x1, tx-dly 0, clock 40000000
aml_sd_retry_refix[983]:delay = 0x0,gadjust =0x52000
[mmc_startup] mmc refix success
init_part() 297: PART_TYPE_AML
[mmc_init] mmc init success
skip dtb signature check
start dts,buffer=0000000073e62360,dt_addr=0000000073e62360
get_partition_from_dts() 71: ret 0
parts: 4
00: recovery 0000000004000000 1
01: boot 0000000002000000 1
set has_boot_slot = 0
02:dreambox-rootfs 0000000100000000 1
03:dreambox-data ffffffffffffffff 4
init_part() 297: PART_TYPE_AML
eMMC/TSD partition table have been checked OK!
crc32_s:0x1577dad == storage crc_pattern:0x1577dad!!!
crc32_s:0xee152b83 == storage crc_pattern:0xee152b83!!!
crc32_s:0x7fd3b243 == storage crc_pattern:0x7fd3b243!!!
mmc env offset: 0x7400000
In: serial
Out: serial
Err: serial
reboot_mode=cold_boot
itest - return true/false on integer compare
Usage:
itest [.b, .w, .l, .s] [*]value1 <op> [*]value2
[store]To run cmd[emmc dtb_read 0x1000000 0x40000]
_verify_dtb_checksum()-2755: calc 1cc15c8c, store 1cc15c8c
_verify_dtb_checksum()-2755: calc 1cc15c8c, store 1cc15c8c
dtb_read()-2972: total valid 2
update_old_dtb()-2953: do nothing
amlkey_init() enter!
[EFUSE_ERR]f(efuse_usr_api_init_dtb)L60:not find /efusekey node [FDT_ERR_NOTFOUND].
[KM]Error:f[keymanage_efuse_init]L38:efuse init failed
[KM]Error:f[key_unify_init]L177:Device[1] init failed, err=39
vpu: clk_level in dts: 7
vpu: vpu_power_on
vpu: set clk: 666667000Hz, readback: 666666667Hz(0x100)
vpu: vpu_module_init_config
vpp: vpp_init
vpp: g12a/b osd1 matrix rgb2yuv ..............
vpp: g12a/b osd2 matrix rgb2yuv..............
vpp: g12a/b osd3 matrix rgb2yuv..............
cvbs: cpuid:0x29
lcd: error: not find /backlight node: FDT_ERR_NOTFOUND
lcd: error: failed to get key_valid
lcd: detect mode: tablet, key_valid: 0
lcd: failed to get lcd_cpu_gpio_names
lcd: load config from dts
lcd: pinctrl_version: 2
lcd: use panel_type=lcd_5
lcd extern: load config from dts
lcd extern: add driver mipi_default(0)
lcd extern: aml_lcd_extern_probe ok
lcd: bl: no backlight exist
set lcd bl to 0
set lcd bl to 200
tpm activate
01 01: 19
02 01: 00
03 04: 00 00 3a b0
06 08: 32 30 32 30 30 36 31 33
07 0f: 34 36 31 33 32 35 30 30 30 30 31 35 30 32 34
05 04: 01 01 01 01
08 01: 00
04 06: 00 09 34 4b 43 ac
10 08: c4 c3 63 34 07 05 8d 96
11 10: 18 0b cf f3 17 44 ca 8f 9f 17 e6 7c 1a c3 91 58
ff 01: 38
card in
co-phase 0x2, tx-dly 0, clock 400000
co-phase 0x2, tx-dly 0, clock 400000
co-phase 0x2, tx-dly 0, clock 400000
co-phase 0x2, tx-dly 0, clock 400000
co-phase 0x2, tx-dly 0, clock 40000000
aml_sd_retry_refix[983]:delay = 0x0,gadjust =0x192000
adj retry sampling point:(25)->(24)[mmc_startup] mmc refix success
init_part() 282: PART_TYPE_DOS
[mmc_init] mmc init success
sdcard label: DREAMBOOT
DREAMBOOT label on sdcard
reading AUTOEXEC.IMG
** Unable to read file AUTOEXEC.IMG **
cannot load AUTOEXEC.IMG
Normal bootup
Net: dwmac.ff3f0000
Hit Enter or space or Ctrl+C key to stop autoboot -- : 0
reading dmtwo.img
** Unable to read file dmtwo.img **
dreambox_two#Lösung von 60plus
Im u-boot fehlen die Einträge run boot_from_flash; run recovery_from_flash;
Im seriellen Zugang den Bootvorgang mit Strg+c unterbrechen und im Putty folgendes eingeben
setenv bootcmd 'run boot_android_from_sdcard; run boot_from_flash; run recovery_from_flash;'
Enter, dann saveenv Enter und zum Schuß reboot
Danke heute hatte ich das gleiche Problem und habe Uboot neu aufgebaut.
